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1.6.2 Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64
bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue in the CPU.
The BCU incorporates a DRAM controller (DRAMC), page ROM controller, and DMA controller (DMAC).
(a) DRAM controller (DRAMC)
This controller generates the RAS, UCAS and LCAS signals (2CAS control) and controls DRAM access.
It is compatible with high-speed DRAM and EDO DRAM. When accessing DRAM, there are 2 types of
cycle; normal access (off page) and page access (on page).
Also, it includes a refresh function that is compatible with the CBR refresh cycle.
(b) Page ROM controller
This controller is compatible with ROM that includes a page access function.
It performs address comparisons with the immediately preceding bus cycle and executes wait control for
normal access (off page)/page access (on page). It can handle page widths of 8 to 64 bytes.
(c) DMA controller (DMAC)
This controller transfers data between memory and I/O in place of the CPU.
There are two address modes, flyby (1 cycle) transfer, and 2-cycle transfer. There are three bus modes,
single transfer, single step transfer, and block transfer.
(3) ROM
The µ PD703101 and 703101A have on-chip mask ROM (96 KB), the µ PD703102 and 703102A have on-chip
mask ROM (128 KB), and the µ PD70F3102 and 70F3102A have on-chip flash memory (128 KB). The
µ PD703100 and 703100A do not include on-chip memory.
During instruction fetch, these memories can be accessed from the CPU in 1 clock cycles.
If the single-chip mode 0 or flash memory programming mode is set, memory mapping is done from address
00000000H, and if single-chip mode 1 is set, from address 00100000H. If ROM-less mode 0 or 1 is set,
access is impossible.
(4) RAM
4 KB of RAM is mapped from address FFFFE000H. During instruction fetch, data can be accessed from the
CPU in 1-clock cycles.
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CHAPTER 1 INTRODUCTION
User's Manual U12688EJ4V0UM00
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