Initialization - NEC V850E/MS1 UPD703100 User Manual

(1) Receiving the reset signal
RESET (input)
Internal system
reset signal
Note The internal system reset signal continues in the active state for at least 4 system clock cycles after
reset clear timing by the RESET signal.
(2) Reset during power on
In the reset operation during power on (when the power is turned on), in accordance with the low-level width of
the RESET signal, it is necessary to secure an oscillation stabilization time of 10 ms or greater from power rise
to the reception of the reset.
HV
DD
RESET (input)

13.3 Initialization

The initial values of the CPU, internal RAM and internal peripheral I/O after reset are shown in Table 13-2.
Initialize the contents of each register as necessary during program operation. Particularly, the registers shown
below are related to system settings, so set them as necessary.
{ Power save control register (PSC): Sets the functions of pins X1 and X2, the operation of the CLKOUT pin, etc.
{ Data wait control register (DWC): Sets the number of data wait states.
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CHAPTER 13 RESET FUNCTIONS
Analog
delay
Eliminate as a noise
acceptance
Oscillation stabilization
time
User's Manual U12688EJ4V0UM00
Analog Analog
delay delay
Note
∆ ∆
Reset Reset
release
Analog delay
∆
Reset release