B.2 Instruction Set (in Alphabetical Order)
Mnemonic
Operand
ADD
reg1,reg2
imm5,reg2
ADDI
imm16,reg1,reg2
AND
reg1,reg2
ANDI
imm16,reg1,reg2
Bcond
disp9
BSH
reg2,reg3
BSW
reg2,reg3
CALLT
imm6
CLR1
bit#3, disp16[reg1]
reg2,[reg1]
CMOV
cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i
cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R R R R R
CMP
reg1,reg2
imm5,reg2
CTRET
DI
434
APPENDIX B INSTRUCTION SET LIST
Op Code
r r r r r 0 0 1 1 1 0 R R R R R
GR[reg2]←GR[reg2]+GR[reg1]
r r r r r 0 1 0 0 1 0 i i i i i
GR[reg2]←GR[reg2]+sign-extend(imm5)
r r r r r 1 1 0 0 0 0 R R R R R
GR[reg2]←GR[reg1]+sign-extend(imm16)
i i i i i i i i i i i i i i i i
r r r r r 0 0 1 0 1 0 R R R R R
GR[reg2]←GR[reg2]AND GR[reg1]
r r r r r 1 1 0 1 1 0 R R R R R
GR[reg2]←GR[reg1]AND zero-extend(imm16)
i i i i i i i i i i i i i i i i
ddddd1011dddc ccc
if conditions are satisfied
Note 1
then PC←PC+sign-extend(disp9)
r r r r r 1 1 1 1 1 1 0 0 0 0 0
GR[reg3]←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
wwwww01101000010
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
r r r r r 1 1 1 1 1 1 0 0 0 0 0
GR[reg3]←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
wwwww01101000000
[reg2] (23 : 16) ll GR[reg2] (31 : 24)
0 0 0 0 0 0 1 0 0 0 i i i i i i
CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Half-word))
10bbb111110RRRRR
adr←GR[reg1]+sign-extend(disp16)
←Not(Load-memory-bit(adr,bit#3))
Z flag
dddddddddddddddd
Store-memory-bit(adr,bit#3,0)
r r r r r 1 1 1 1 1 1 R R R R R
adr←GR[reg1]
←Not(Load-memory-bit(adr,reg2))
Z flag
0000000011100100
Store-memory-bit(adr,reg2,0)
if conditions are satisfied
wwwww011000cccc0
then GR[reg3]←sign-extended(imm5)
else GR[reg3]←GR[reg2]
if conditions are satisfied
wwwww011001cccc0
then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
r r r r r 0 0 1 1 1 1 R R R R R
result←GR[reg2]–GR[reg1]
r r r r r 0 1 0 0 1 1 i i i i i
result←GR[reg2]–sign-extend(imm5)
0000011111100000
PC←CTPC
0000000101000100
PSW←CTPSW
0000011111100000
PSW.ID←1
0000000101100000
User's Manual U12688EJ4V0UM00
Operation
1
When conditions
are satisfied
Note 2
1
When conditions
are not satisfied
Note 3
Note 3
1
(1/6)
Execution
Flags
Clock
i
r
l
CY OV S
Z SAT
×
×
×
×
1
1
1
×
×
×
×
1
1
1
×
×
×
×
1
1
1
×
×
1
1
0
×
1
1
1
0
0
2
2
2
Note 2
Note 2
1
1
×
×
×
1
1
1
0
×
×
×
1
1
1
0
4
4
4
×
3
3
3
Note 3
Note 3
×
3
3
3
Note 3
Note 3
1
1
1
1
1
1
×
×
×
×
1
1
×
×
×
×
1
1
1
3
3
3
R
R
R
R
R
1
1
1