Table 4.3.2 Port 2 Pin State (Single-Chip Mode) - Fujitsu F2MC-8L MB89620 Series Hardware Manual

4.3 Port 2
4.3.2 Operation of Port 2
This section describes the operations of the port-2 in single-chip mode.
Operation of Port 2 (Single-chip Mode)
n
Operation as an output-only port
l
• Writing data to the PDR2 register stores the data in the output latch and outputs the data to
the pin via the output buffer.
• Reading the PDR2 register always returns the output latch data.
Operation at reset
l
Resetting the CPU in single-chip mode forcibly sets the buffer to "OFF" and sets the pins to the
high-impedance state. At the time when the CPU fetch the mode data (00
as part of the reset operation, output is enabled and the output ports output the "L" level.
Note: A reset initializes the PDR2 register bits to all "0"s so that the pins output the "L" level.
l Operation in stop mode
The output buffer is forcibly set to "OFF" and the pins go to the high-impedance state if the pin
state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop mode.
Table 4.3.2 lists the port 2 pin states.

Table 4.3.2 Port 2 Pin State (Single-chip Mode)

P20/BUFC to P27/ALE
SPL
MOD0, MOD1 : Mode pins
Hi-z
Note:
A pull-up resistor cannot be set to port 2 as an option (without a pull-up resistor).
MB89620 series
Normal operation
Pin name
Stop mode (SPL=0)
Output-only ports
: Pin state specification bit in the standby control register (STBC)
: High impedance
Stop mode
Sleep mode
(SPL=1)
) from internal ROM
H
Reset
(MOD0, MOD1 = V
Hi-z Hi-z
CHAPTER 4 I/O PORTS
, V )
SS SS
97