Infineon Technologies CYPRESS Traveo Series Manual page 297

Page Section
13 CHAPTER 3:
Product
Description
3.2.1. Ethernet
Document Number: 002-10634 Rev. *J
Deleted the shading parts as below:
Error)
Direct Memory Access Interface.
- partial store and forward
- force max amba burst tx/rc
- Priority Queueing (Screening)
External FIFO Interface
Additional Low Latency TX FIFO Interface for DMA configurations
MAC Transmit Block
- half-duplex
- collision
- back_pressure
MAC Filtering Block
- external address match
- VLAN tag
- Wakeup On Lan
IEEE 1588 and IEEE 802.1AS Support
MAC PFC Priority Based Pause Frame Support
Energy Efficient Ethernet support
LPI Operation in Cadence IP
802.1Qav Support – Credit Based Shaping
PHY Interface
- GMII
- SGMII
- TBI
10/100/1000 Operation
- 10 M
- 1000 M
SGMII Operation
Jumbo Frames
Physical Control Sub-Layer
Correct)
External FIFO Interface
Additional Low Latency TX FIFO Interface for DMA configurations
MAC Transmit Block
- half-duplex
- collision
- back_pressure
MAC Filtering Block
- external address match
- Wakeup On Lan
Energy Efficient Ethernet support
LPI Operation in Cadence IP
PHY Interface
- GMII
- SGMII
- TBI
10/100/1000 Operation
- 1000 M
SGMII Operation
Jumbo Frames
Physical Control Sub-Layer
Change Results
Functions
Functions
S6J3350 Series
Remark
Remark
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