Infineon Technologies CYPRESS Traveo Series Manual page 12

Feature
Embedded
Program/Work Flash
Memory
Internal Power Domain
Power Supply
Low Voltage Detection
Low voltage detection for
RAM retention (RVD)
Resource inter-connect
I/O Ports
A/D Converter
CRC
Programmable CRC
Document Number: 002-10634 Rev. *J
Embedded Program Flash can be accessed with 0-wait-cycle if CPU frequency is 80 MHz or less.
0-wait-cycle: 80 MHz or less.
1-wait-cycle: 160 MHz or less.
2-wait-cycle: more than 160 MHz.
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5 MHz or less.
6-wait-cycle: 80 MHz or less.
12-wait-cycle: 160 MHz or less.
The wait-cycle setting see the Traveo™ Platform Hardware Manual in details.
The CLK_FCLK maximum frequency should be referred in 9.1.4.3.
Erase suspend is supported. Reading and writing to the other sector are possible when Flash
Erase is suspended.
Serial Flash programing and Parallel Flash programing are supported.
Margin mode is not supported.
PD1: Always ON
PD2: Cortex R5F platform/ additional peripherals
PD4: Backup RAM in Always On domain
PD6: Peripherals in Always On domain
* The chapter of the block diagram explains in detail.
5 V, and 3 V, 1.2 V external power supply is required.
Built in LDO provides internal power supply for Always On region (PD1).
1.2 V external power supply control pin is supported.
3 V external power supply could be controlled by GPIO.
There are constraints of power on/off sequence.
LVD for external voltage is supported.
LVD for internal voltage is supported.
See 9.1.4.11 and 9.1.4.12 .
RVD for RAM retention is effective during the standby mode only. That is, it is only for the
Backup RAM of 32 KB that the function is available.
The output signal of some resources can be inputted to the other resource.
5 V general purpose I/O
3 V general purpose I/O
Multi input level and multi output drivability
Pull-up, pull-down function is available.
Resource input and output is multiplexed.
+B input is allowed many pins of 3.3 V, 5 V and 3.3 V/5 V I/O domain.
12 bit resolution, 2 unit(Unit0 is possible to select channels 0-31. Unit1 is possible to select
channels 32-63.)
64 channels of analog input for TEQFP208
48 channels of analog input for TEQFP176
35 channel of analog input for TEQFP144
External trigger and timer trigger are available.
The description of the A/D converter function should be referred in the S6J3300 Hardware
Manual. Though the chapter of I/O port in Traveo™ Platform Hardware Manual describes
another A/D converter function, do not refer it.
A/D Channel Control Register (ADC12Bn_CHCTRL0)[bit5:0] ANIN[5:0]: Analog Input Selection
bits.
This register setting is possible of channel 0-31 (the register value is 00_0000 to 01_1111).
AN39 to AN63 are not support for S6J335xxAx, S6J335xxCx, S6J335xxEx, and S6J335xxGx
option.
See the Traveo™ Platform Hardware Manual in detail.
DMA support
Description
S6J3350 Series
Page 11 of 307