Infineon Technologies CYPRESS Traveo Series Manual page 217

External bus interface timing
9.1.4.14
Clock output timing
Parameter Symbol
Cycle time
Clock high width *1
Clock low width *2
*1: If division-ratio is even value, dH is equivalent to 0.5.
Otherwise, dH is calculated as the following.
dH = The number rounding "division-ratio x 0.5" down to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dH is calculated as 0.429.
*2: If division-ratio is even value, dL is equivalent to 0.5.
Otherwise, dL is calculated as the following.
dL = The number rounding "division-ratio x 0.5" up to the nearest integer / division-ratio
division-ratio is multiplication value among SYSDIV bit, HPMDIV bit and EXTBUSDIV bit setting.
ex). Setting SYSDIV to 1-division, HPMDIV to 7-division, EXTBUSDIV to 1-division, dL is calculated as 0.571.
− Clock output timing
Document Number: 002-10634 Rev. *J
(T
Pin Name
t MCLK
CYC
t MCLK
CHCL
t MCLK
CLCH
: Recommended operating conditions, Vcc53 = 5.0 V ± 10 %, VSS = 0.0 V)
A
Conditions
Min
2mA is 62.5
selected in
d t
H
ODR bit in
PPC_PCFGR
d t
L cyc
register.
S6J3350 Series
(External load capacitance 16 pF)
Value
Unit
Max
- ns
- 7 d t + 7 ns
cyc H cyc
- 7 d t + 7 ns
L cyc
Remarks
Page 216 of 307