Infineon Technologies CYPRESS Traveo Series Manual page 233

Power and Reset Sequence
9.1.4.19
VCC5 and VCC12 sequence
Parameter
Wait time from LVDH1
level detection to falling
VCC12
VCC12 stabilization
time during power-on
VCC5
PSC_1
VCC12
RSTX
Note:
−
VDLAT VRDLAT, VRDLBT and VRHYS are referred to
VOH7 is referred to "9.1.3 DC
−
LVDH1 reset need to be "always enable". For details, see the Traveo™ Platform Hardware Manual.
−
The above sequence needs not to be applied in the following cases the application enters PSS mode:
"VCC12 is controlled by PSC_1 at entry and exit from PSS mode"(Normal Sequence).
Document Number: 002-10634 Rev. *J
Symbol Pin Name
t VCC12
FV12
t VCC12
RV12
V
DLAT
t
FV12
V
RDLAT
No timing specification of VCC12 and RSTX
Characteristics".
(T : Recommended operating conditions, VSS = 0.0 V)
A
Conditions
Min
0.6
-
- -
V
"9.1.4.11 Low Voltage Detection (External
S6J3350 Series
Value
Unit
Max
- ms
14.2 ms
V
OH7
t
RV12
+V
RDLBT RHYS
Voltage)".
Remarks
−
−
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