Infineon Technologies CYPRESS Traveo Series Manual page 290

Page Section
10
3: Product Description
3.2. Product
Description
11
3: Product Description
3.2. Product
Description
12
3: Product Description
3.2. Product
Description
12
3: Product Description
3.2. Product
Description
Document Number: 002-10634 Rev. *J
Feature: Reset
Error)
Based on Cortex R5F platform
Following resets are not mounted on this device.
INITX
−
SRSTX
−
Correct)
RSTX pin + MD pin simultaneous assert INITX (Same as INITX pin input)
Occurrence factor: Simultaneously inputting "L" level to RSTX pin and inputting "L" level to MD pin
−
Release factor: Inputting "H" level to RSTX pin
−
See the Traveo™ Platform Hardware Manual in detail.
Following resets are not mounted on this device.
SRSTX (and nSRST pin)
−
The product series does not support EX5VRST and writing EX5VRSTCNT bits in SYSC0_SPECFGR
has no effect.
Feature: PLL / SSCG PLL
Error)
Down spread mode is only supported and available.
Correct)
Product supports down spread and center spread modes with the conditions defined in 9.1.4.3 "Internal Clock
Timing".
Feature: Embedded Program/Work Flash Memory
Error)
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less.
7-wait-cycle: 80MHz or less.
13-wait-cycle: 160MHz or less.
Correct)
Work Flash can be accessed with 0-wait-cycle if CPU frequency is 12.5MHz or less.
6-wait-cycle: 80MHz or less.
12-wait-cycle: 160MHz or less.
Feature: Security
Error)
Chip erase function is available for flash memory.
The function of "MK_CEER" is not supported. (MK_CEER = not selectable)
For details, see the platform manual and chapter "Security"
Correct)
-
Change Results
S6J3350 Series
Page 289 of 307