Infineon Technologies CYPRESS Traveo Series Manual page 135

Register
Resource
(Offset)
RIC_RE
SIN638 RXCLK
(0x04FC)
RIC_RE
SIN639 TXCLK
(0x04FE)
RIC_RE
SIN685 ADTRG0
(0x055A)
RIC_RE
SIN686 ADTRG1
(0x055C)
Notes:
−
When both GPIO_PORTEN.GPORTEN and PPC_PCFGR.PIE are configured as 0, the input signal is disconnected and
external interrupt cannot be detected. During disconnecting, I/O internally outputs "low" to internal logic, and if ELVR is
configured as low-level-detection, falling-edge-detection, or both-edge-detection it will be detected as external interrupt with
EIRR=1.
−
"Set 0" (Set 1) means that "0" ("1") is inputted.
−
OCUx_MODn is described as MODn pin in Traveo™ Platform Hardware Manual.
Document Number: 002-10634 Rev. *J
RESSEL
[3:0]
0
/PORT
8
SEL[3:0]
RESSEL
-
(0-7)
RESSEL
-
(8-15)
PORTSEL
P0_17 P4_00
(0-7)
PORTSEL
-
(8-15)
RESSEL
-
(0-7)
RESSEL
-
(8-15)
PORTSEL
P0_20 P4_03
(0-7)
PORTSEL
-
(8-15)
RESSEL
-
(0-7)
RESSEL
-
(8-15)
PORTSEL
P1_16 P2_10
(0-7)
PORTSEL
-
(8-15)
RESSEL
-
(0-7)
RESSEL
-
(8-15)
PORTSEL
P4_22 P1_08
(0-7)
PORTSEL
-
(8-15)
Source for Resource Input
1 2 3
9 10 11
- - -
- - -
- -
- - -
- - -
- - -
- -
- - -
- - -
- - -
- -
- - -
- - -
- - -
P2_11 -
- - -
S6J3350 Series
4 5 6
12 13 14
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
Page 134 of 307
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