Infineon Technologies CYPRESS Traveo Series Manual page 13

Feature
Base Timer
Reload Timer
I/O Timer
Up/Down Counter
Multi-Functional Serial
(MFS)
CAN-FD
Real Time Clock (RTC)
with auto-calibration
DDR High Speed SPI
Hyper BUS I/F
External Interrupt Capture
Unit (EICU)
Ethernet AVB
SHE
Source Clock Timer
External BUS
Power Supply Control
(PSC)
Document Number: 002-10634 Rev. *J
See the Traveo™ Platform Hardware Manual in detail.
A unit consists of a pair of 16bit base timers. 32 units, that is, 64 channels of base timers are
available.
See the Traveo™ Platform Hardware Manual in detail.
See the Traveo™ Platform Hardware Manual in detail.
See the Traveo™ Platform Hardware Manual in detail.
See the Traveo™ Platform Hardware Manual in detail.
Only 2 ports of MFS have the dedicated I/O for I
See I 2 C timing in 9.1.4.6 Multi-Function Serial
2
The I C is not designed to be hot swappable.
CTS/RTS is not mounted (hardware flow control is not supported for this series.)
Flexible data rate is supported.
16 KB/ch of message RAM is available.
The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function
of the message RAM is not supported for this device. Therefore, CAN FD ECC Error Insertion
Control Register (FDFECR) is not writeable.
See the Traveo TM Platform Hardware Manual in detail.
ch.0: HSSPI as a MCU peripheral
ch.0: Hyper Bus as a MCU peripheral
The following register is not supported and cannot be used.
Controller Status Register (HYPERBUSIn_CSR)
−
Interrupt Enable Register (HYPERBUSIn_IEN)
−
Interrupt Status Register (HYPERBUSIn_ISR)
−
Write Protection Register (HYPERBUSIn_WPR)
−
Test Register (HYPERBUSIn_TEST)
−
GPO signal can only be used for "Internal Control example by GPO" in this product, that is, it can
select using HyperBus of Traveo™ Platform Hardware Manual.
TM
See the Traveo Platform Hardware Manual in detail.
10/100 Mbps
MII-Interface
Supports Audio-Video Bridging (AVB)
See the Traveo™ Platform Hardware Manual in detail.
See the Traveo™ Platform Hardware Manual in detail.
TEQFP208: 22 bit address and 16 bit data
TEQFP176: 22 bit address and 16 bit data
TEQFP144: 15 bit address and 8 bit data
PSC (PSC_1) output is used for external 1.2 V power supply module control and automatically
switched with the following condition.
"High": Request to supply VCC12
- "Power ON Reset" is released
- CPU wakes up from PSS shutdown mode
"Low": Request to stop supplying VCC12
- CPU transfers from RUN mode to PSS shutdown mode.
For timing chart of output signals include PSC in detail, see the "S6J3300 Hardware Manual"
and chapter "State Transition"
Description
2
C.
in detail.
S6J3350 Series
Page 12 of 307