Infineon Technologies CYPRESS Traveo Series Manual page 281

Page Section
173 9. Electric
Characteristics
9.1.2
Recommended
operating condition
174 9. Electric
Characteristics
9.1.2
Recommended
operating condition
Document Number: 002-10634 Rev. *J
Error)
− In the case of use in VCC5 = AVCC5 = DVCC of conditions, please launch the power supply in
the following sequence.
Required power supply sequence is the following:
VCC5 -> [DVCC or VCC53 or AVCC5 or VCC3] -> VCC12
Note that power supplies inside "[ ]" can be turned on in arbitrary order.
Corresponding Part number is S6J335xxSC or S6J335xxUC or S6J335xxTC or S6J335xxVC or
S6J335xxBC or S6J335xxDC or S6J335xxFC or S6J335xxHC.
− In the case of use in VCC5 = AVCC5 < DVCC of conditions, please launch the power supply in
the following sequence.
Required power supply sequence is the following:
VCC5 -> DVCC -> [VCC53 or AVCC5 or VCC3] -> VCC12.
Note that power supplies inside "[ ]" can be turned on in arbitrary order.
Corresponding Part number is S6J335xxAC or S6J335xxCC or S6J335xxEC or S6J335xxGC.
Correct)
- Required power supply sequence is the following:
{VCC5 -> AVCC5} -> [DVCC, VCC12, VCC3, AVCC3_DAC]
Note that power supplies inside "[ ]" can be turned on in arbitrary order and "{ }" can be turned on in
shown sequence or simultaneously.
Error)
-
Correct)
Note:
−TA: Ambient temperature (JEDEC)
−TC: Case temperature (JEDEC), the maximum measured temperature of package case top.
−Both rating of TA and TC should simultaneously be satisfied as maximum operation temperature.
−The following condition should be satisfied in order to facilitate heat dissipation.
1. Four or more layers PCB should be used.
2. The area of PCB should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or
more. (JEDEC standard)
3. One layer of middle layers at least should be used for dedicated layer to radiate heat with
residual copper rate 90% or more. The layer can be used for system ground.
4. 35% or more of the die stage area which is exposed at back surface of package should be
soldered to a part of 1st layer.
5. The part of 1st layer should be connected to the dedicated heat radiation layer with more than 10
thermal via holes.
Example thermal via holes on PCB
<Figure>
− The above figure is a schematic diagram showing PCB in section.
− Thermal via holes should closely be placed and aligned with lands.
− It is recommended to connect the land pattern to the VSS-ground level (GND plan of inner layer
bellow the MCU) as thermal heat sink.
Change Results
S6J3350 Series
Page 280 of 307