Infineon Technologies CYPRESS Traveo Series Manual page 218

Common timing between read and write
Parameter Symbol
Cycle time
(without MRDY)
Cycle time
(with MRDY)
CS delay time
Address delay time
RDY setup time
RDY hold time
Notes: This is Target Spec.
− External bus I/F common timing
Document Number: 002-10634 Rev. *J
Pin Name
t MCLK
CYC
t MCLK
CYC
MCLK,
t
CSO
MCSX0 to MCSX3
MCLK,
t
AO
MAD00 to MAD23
t MCLK, MRDY
RDYS
t MCLK, MRDY
RDYH
(T : Recommended operating conditions, Vcc53 = 5.0 V ± 10 %, V
A
Conditions
2mA is selected in
ODR bit in
PPC_PCFGR register.
"CMOS Schmitt input"
and "Disable noise
filter" are selected in
PPC_PCFGR register.
S6J3350 Series
(External load capacitance 16 pF)
Value
Unit
Min Max
62.5 - ns
62.5 - ns
0.5 18 ns
0.5 18 ns
21 - ns
0 - ns
= 0.0 V)
SS
Remarks
If using MRDY,
set MCLK to
20 MHz or
less.
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