Infineon Technologies CYPRESS Traveo Series Manual page 257

Page Section
229 9.Electric
Characteristics
9.1.4.15 DDR-
HSSPI
Document Number: 002-10634 Rev. *J
Revised as below:
Error)
(16-1) DDR-HSSPI Interface Timing (SDR mode)
Parameter Symbol
HSSPI clock cycle
t
cyc
M_SCLK↑ ->
t
delayed sample clock↑
spcnt
M_SDATA -> delayed
sample clock↑
t
isdata
Input setup time
delayed sample clock↑ -
> M_SDATA
t
ihdata
Input hold time
M_SCLK↑ -> M_SDATA
t
Output delay time
oddata
M_SCLK↑ -> M_SDATA
t
Output hold time
ohdata
M_SCLK↑ -> M_SSEL
t
Output delay time
odsel
M_SCLK↑ -> M_SSEL
t
Output hold time
ohsel
Notes: This is Target Spec.
Correct)
(1)DDR-HSSPI Interface Timing (SDR mode)
Parameter Symbol
HSSPI clock cycle
t
cyc
M_SCLK↑ ->
t
delayed sample clock↑ spcnt
M_SDATA ->
M_SLCK↑
t
isdata
Input setup time
M_SCLK↑ ->
M_SDATA
t
ihdata
Input hold time
M_SCLK↑ ->
M_SDATA
t
oddata
Output delay time
M_SCLK↑ ->
M_SDATA
t
ohdata
Output hold time
M_SCLK↑ -> M_SSEL
t
Output delay time
odsel
M_SCLK↑ -> M_SSEL
t
Output hold time
ohsel
Notes: This is Target Spec.
−
SS2CD [1:0] should be configured as 01, 10, or 11.
−
For *1, the delay of the delay sample clock can be configured (DLP function)..
Change Results
Pin Name Conditions
M_SCLK0
-
M_SDATA0_0-3
M_SDATA1_0-3
(CL = 20pF,
M_SDATA0_0-3
M_SDATA1_0-3
I =-10mA,
OL
M_SDATA0_0-3
I =10mA),
OH
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
M_SSEL0, 1
M_SSEL0, 1
Pin Name Conditions
M_SCLK0
-
M_SDATA0_0-3
M_SDATA1_0-3
(CL = 20pF,
M_SDATA0_0-3
M_SDATA1_0-3
I =-10mA,
OL
I =10mA),
M_SDATA0_0-3
OH
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
M_SSEL0, 1
(SS2CD+0.5)*
M_SSEL0, 1
S6J3350 Series
Value
Unit Remarks
Min Max
10 - ns
0 tcyc ns
3.5 - ns
2.0 - ns
- 6.5 ns t
cyc
3.5 - ns
- 5.5 ns t
cyc
4.5 - ns
Value
Unit Remarks
Min Max
10 -
when Quad
ns
20 - Page
Program
0 31.5 ns
*1 - ns
*1 - ns
- t /2 + 2 ns
cyc
t /2 - 3 - ns
cyc
-12.00+
- ns
t
cyc
t - 2 - ns
cyc
Page 256 of 307
-3.5ns
-4.5ns