Infineon Technologies CYPRESS Traveo Series Manual page 265

Page Section
183
9.Electric
Characteristics
9.1.4.3.Internal clock
timing
185
9.Electric
Characteristics
9.1.4.3.internal clock
timing
Document Number: 002-10634 Rev. *J
Revised as below:
Error)
- Note that Ta=125 condition is not supported in this product type.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following
restrictions.
‐On the presumption that the modulation mode of SSCG_PLL is used with down spread,
the MAX value of the frequency is standardized.
‐This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
Correct)
- Note that Ta=125 condition is not supported in this product type.
When using SSCG_PLL output for these internal clock, the MAX value of frequency has the following
restrictions.
‐On the presumption that the modulation mode of SSCG_PLL is used with down spread,
the MAX value of the frequency is standardized.
‐This means that MAX value of frequency is the maximum value when SSCG_PLL was modulated.
‐"Unused" means a clock source which doesn't have any supply destinations. Configure it as disable with
performing at the lower clock frequency than the described maximum.
Added Oscillation clock frequency as below:
Correct)
Main
Multiplied
Clock
4 2
Oscillation
clock
8 4
frequency
[MHz]
16 8
Change Results
Internal Operation Clock Frequency
Multiplied Multiplied
by 1 by 2
4 8 ...
8 16 ...
16 32 ...
S6J3350 Series
PLL Clock
Multiplied Multiplied
by 15 by 30 by 40
60 120 160
120 240
240
Page 264 of 307
Multiplied
by 60
240