Infineon Technologies CYPRESS Traveo Series Manual page 184

Parameter Symbol
Serial clock
t
cycle time
SCK ↓ → SOT
t
SHOVI
delay time
Valid SIN → SCK ↑
t
setup time
SCK ↑→ Valid SIN
t
hold time
Serial clock
t
"H" pulse width
Serial clock
t
"L" pulse width
SCK ↑ → SOT
t
SHOVE
delay time
Valid SIN → SCK ↓
t
setup time
SCK ↓ → Valid SIN
t
hold time
SCK falling time
SCK rising time
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
−
This table provides the alternate current standard for CLK synchronous mode.
−
CL is the load capability value connected to the pin at the test time.
−
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the Traveo™ Platform Hardware Manual.
Document Number: 002-10634 Rev. *J
Pin Name
SCK2_0, SCK3_0
SCYC
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
IVSLI
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
SLIXI
SCK0 to SCK4,
SCK8 to SCK12
SHSL
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12
SLSH
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0 to SCK4,
IVSLE
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SLIXE
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
t SCK8 to SCK12,
F
SCK16 to SCK17
SCK0 to SCK4,
t SCK8 to SCK12,
R
SCK16 to SCK17
Conditions
Min
2t
CLK_LCPnA
Master
-7.5
Mode
(CL = 20pF,
I = -10mA,
10
OL
I = 10mA)
OH
0
4t
CLK_LCPnA
4t
CLK_COMP
4t
CLK_LCPnA
4t
CLK_COMP
-
Slave
Mode
(CL = 20pF,
I = -5mA,
OL
10
I = 5mA)
OH
10
-
-
S6J3350 Series
Value
Unit
Max
*1
- ns
+7.5 ns
- ns
- ns
*1
- ns
- ns
*1 - ns
- ns
40 ns
- ns
- ns
5 ns
5 ns
Page 183 of 307
Remarks
-