Infineon Technologies CYPRESS Traveo Series Manual page 189

(4) SPI Supported (SCR: SPI = 1), and Mark Level "L" of Serial Clock Output (SMR: SCINV = 1)
(T
A
Parameter Symbol
Serial clock
t
cycle time
SCK ↓ -> SOT
t
delay time
Valid SIN -> SCK ↑
t
setup time
SCK ↑ -> Valid SIN
t
hold time
SOT -> SCK ↑
t
SOVHI
delay time
Serial clock
t
cycle time
SCK ↓ -> SOT
t
delay time
Valid SIN -> SCK ↑
t
setup time
SCK ↑ -> Valid SIN
t
hold time
SOT -> SCK ↑
t
SOVHI
delay time
Document Number: 002-10634 Rev. *J
: Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, Vcc5 = DVcc = 5.0 V ± 10 % / 3.3 V ± 0.3 V,
Vcc53 = 5.0 V ± 10 % / 3.3 V ± 0.3V, V
Pin Name
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCYC
SCK8 to SCK12
SCK16 to SCK17
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SLOVI
SOT0, SOT1, SOT2_1,
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
IVSHI
SCK8 to SCK12,
SCK16 to SCK17
SIN0, SIN1, SIN2_1,
SIN3_1, SIN4,
SHIXI
SIN8 to SIN12,
SIN16 to SIN17
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0, SOT1, SOT2_1,
SOT3_1, SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK16 to SCK17
SOT16 to SOT17
SCK2_0, SCK3_0
SCYC
SCK2_0, SCK3_0,
SLOVI
SOT2_0, SOT3_0
IVSHI
SCK2_0, SCK3_0,
SIN2_0, SIN3_0
SHIXI
SCK2_0, SCK3_0,
SOT2_0, SOT3_0
SS
Conditions
Min
8t
CLK_LCPnA
8t
CLK_COMP
-30
Master
Mode
40
(CL = 20pF,
I = -5mA,
OL
I = 5mA)
OH
0
*1
4t
CLK_LCPnA
30
4t -30
CLK_COMP
2t
CLK_LCPnA
-7.5
Master
Mode
10
(CL = 20pF,
I = -10mA,
OL
0
I = 10mA)
OH
*1
t
CLK_LCPnA
7.5
S6J3350 Series
= DV = 0.0 V, V 12 = 1.15 V ± 0.06 V)
SS CC
Value
Unit
Max
*1 - ns
- ns
+30 ns
- ns
- ns
-
- ns
- ns
*1 - ns
+7.5 ns
- ns
- ns
-
- ns
Page 188 of 307
Remarks
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