Infineon Technologies CYPRESS Traveo Series Manual page 258

Page Section
231 9.Electric
Characteristics
9.1.4.15 DDR-
HSSPI
Document Number: 002-10634 Rev. *J
Revised as below:
Error)
(16-2) DDR-HSSPI Interface Timing (DDR mode)
Parameter Symbol
HSSPI clock cycle
t
cyc
M_SCLK↑ ->
t
delayed sample clock↑
spcnt
M_SDATA -> delayed
sample clock↑
t
isdata
Input setup time
delayed sample clock↑
-> M_SDATA
t
ihdata
Input hold time
M_SCLK↑ ->
M_SDATA
t
oddata
Output delay time
M_SCLK↑ ->
M_SDATA
t
ohdata
Output hold time
M_SCLK↑ -> M_SSEL
t
Output delay time
odsel
M_SCLK↑ -> M_SSEL
t
Output hold time
ohsel
Notes: This is Target Spec.
Correct)
(2)DDR-HSSPI Interface Timing (DDR mode)
Parameter Symbol
HSSPI clock cycle
t
cyc
M_SCLK↑ ->
t
delayed sample clock↑
spcnt
M_SDATA -> M_SLCK↑
t
Input setup time
isdata
M_SLCK↑ -> M_SDATA
t
Input hold time ihdata
M_SCLK↑ -> M_SDATA
t
Output delay time
oddata
M_SCLK↑ -> M_SDATA
t
Output hold time
ohdata
M_SCLK↑ -> M_SSEL
t
Output delay time odsel
M_SCLK↑ -> M_SSEL
t
Output hold time ohsel
Notes: This is Target Spec.
−
SS2CD [1:0] should be configured as 01, 10, or 11.
−
For *1, the delay of the delay sample clock can be configured (DLP function)
Change Results
Pin Name Conditions
M_SCLK0
M_SDATA0_0-3
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3 (CL = 20pF,
I =-10mA,
OL
M_SDATA0_0-3
I =10mA),
M_SDATA1_0-3
OH
M_SDATA0_0-3
M_SDATA1_0-3
M_SSEL0, 1
M_SSEL0, 1
Pin Name Conditions
M_SCLK0
M_SDATA0_0-3
M_SDATA1_0-3
M_SDATA0_0-3
M_SDATA1_0-3
(CL = 20pF,
I =-10mA,
M_SDATA0_0-3
OL
M_SDATA1_0-3
I =10mA),
OH
M_SDATA0_0-3
M_SDATA1_0-3
M_SSEL0, 1
(SS2CD+0.5)*t
M_SSEL0, 1
0.75*t
S6J3350 Series
Value
Unit
Min Max
10 - ns
0 tcyc ns
1.0 - ns
1.0 - ns
- 3.5 ns
1.5 - ns
- 7.0 ns
3.0 - ns
Value
Unit
Min Max
12.5 - ns
0 31.5 ns
*1 - ns
*1 - ns
t /4 +
cyc
- ns
1.5
Tcyc/4 - 1.0 - ns
-15.75+
- ns
cyc
- 2.0 - ns
cyc
Page 257 of 307
Remarks
t /2-1.5ns
cyc
t -3.0ns
cyc
Remarks