Infineon Technologies CYPRESS Traveo Series Manual page 171

AC Characteristics
9.1.4
Source Clock Timing
9.1.4.1
Parameter
Source oscillation
clock frequency
Source oscillation
clock cycle time
CAN PLL jitter
(when locked)
Internal Slow CR
oscillation frequency
Internal Fast CR
oscillation frequency
Notes:
−
The maximum/minimum values have been standardized with the main clock and PLL clock in use.
−
Jitter of source oscillator must be smaller than 300ppm.
−
Enough evaluation and adjustment are recommended using oscillator on your system board.
− X0 and X1 clock timing
CAN PLL jitter
A time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles.
Ideal clock
Slow
PLL output
Fast
Document Number: 002-10634 Rev. *J
(T : Recommended operating conditions, Vcc5 = 5.0 V ± 10 %, V
A
Symbol Pin Name
F X0, X1
C
t X0, X1
CYL
t -
PJ
F -
CRS
F -
CRF
CYL
Conditions
Min
- 3.6
- 62.5
- -10
- 50
2.40
-
3.20
S6J3350 Series
= DV
SS
Value
Unit
Typ Max
- 16.0 MHz
- 277.8 ns
- 10 ns
100 150 kHz
4.00 5.61- MHz
4.00 4.81 MHz
= AV = 0.0 V)
SS SS
Remarks
Before trim
After trim
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