Infineon Technologies CYPRESS Traveo Series Manual page 199

Parameter Symbol
SCK ↓ → SCS ↑
t
clock switching
SCC
time
*1:
t = SCSTR: CSSU[7:0] x serial chip select timing operating clock
CSSU
*2:
t = SCSTR: CSHD[7:0] x serial chip select timing operating clock
CSHD
*3:
t = SCSTR: CSDS[15:0] x serial chip select timing operating clock
CSDS
*1 *2 *3
For details on , , and above, see the Traveo™ Platform Hardware Manual.
*4 t n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
CLK_LCPnA
Notes:
−
This is the AC characteristic in CLK synchronized mode.
−
CL is the load capacitance applied to pins during testing.
−
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the Traveo™ Platform Hardware Manual
SCS
output
SCK output
SOT
(Normal
synchronous
transfer)
SOT
(SPI
compatible)
Document Number: 002-10634 Rev. *J
Pin Name
SCK0, SCK1, SCK2_1,
SCK3_1, SCK4,
SCK8 to SCK12
SCS0x, SCS1x,
SCS2x_1,
SCS3x_1, SCS4,
SCS8x to SCS12x
SCK16 to SCK17
SCS16x to SCS17x
SCK2_0, SCK3_0,
SCS2x_0, SCS3x_0
V
OH
t
CSSI
V
OL
Conditions
Min
Master
mode
4t
CLK_LCPnA
round
+0
operation
(CL = 20pF,
I = -5mA,
OL
I = 5mA)
OH
4t
CLK_COMP
Master
mode
round
4t
CLK_LCPnA
operation
+0
(CL = 20pF,
I = -10mA,
OL
I = 10mA)
OH
Master mode
S6J3350 Series
Value
Unit
Max
*4 *4
4t
CLK_LCPnA
ns
+15
4t
CLK_COMP
+0 ns
+15
*4 4t *4
CLK_LCPnA
ns
+10
t
CSDI
V
OH
V
OL
t
CSHI
V
OH
Page 198 of 307
Remarks