Infineon Technologies CYPRESS Traveo Series Manual page 222

M_SCLK0
G_SCLK0
delayed
sample clock
G_SDATA0_0-3,
M_SDATA0_0-3,
M_SDATA1_0-3
G_SDATA1_0-3
(input timing)
G_SDATA0_0-3,
M_SDATA0_0-3,
M_SDATA1_0-3
G_SDATA1_0-3
(output timing)
GSSEL0, 1
M_SSEL0,1
(output timing)
Document Number: 002-10634 Rev. *J
t
cyc
V
OH
t
spcnt
V
OH
t t
isdata ihdata
V
IH
valid
V
IL
t
oddata
V
V
t
odsel
V
OH
V
IH
V
IL
OH
valid
OL
V
OH
valid
V
OL
S6J3350 Series
t
ohdata
V
OH
V
OL
t
ohsel
V
OH
V
OL
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