Infineon Technologies CYPRESS Traveo Series Manual page 238

RSTX and MODE Sequence
Parameter
RSTX↑ -> MODE↑
delay time
Reset and mode input
time
Width for reset and
mode input removal
RSTX
MODE
Note:
−
If the sequence given in "VCC5 and VCC12 sequence" and "VCC12 and RSTX Sequence" cannot be applied, this sequence
can be applied.
−
Connect RSTX signal and MODE signal outside of the MCU and shorten the trace length between MCU and these two signal
lines.
−
The following assumptions are made with regard to the workaround described above.
1. After the reset the MCU state is equivalent to the "cold start state" usually reached by power-on-reset.
2. Debugger interface and PC writer interface are not enabled.
3. The RAM retention cannot be guaranteed when applying this workaround
4. Pin PSC_1 will be driven low while RSTX is active (RSTX at low level)
Document Number: 002-10634 Rev. *J
(T : Recommended operating conditions, Vcc5 = 5.0 V ± 10 % / 3.3 V ± 0.3V, VSS = 0.0 V)
A
Symbol Pin Name
RSTX,
tMOD
MODE
RSTX,
tRSTMDL
MODE
0.7*VCC5
0.7*VCC5
tMOD
Value
Conditions
Min
-5
-
10
-
1
RSTX
MODE
tRSTMDL
0.2*VCC5
S6J3350 Series
Unit Remarks
Max
5 ns
−
- us
−
- us
−
0.2*VCC5
Page 237 of 307