Infineon Technologies CYPRESS Traveo Series Manual page 221

DDR-HSSPI
9.1.4.15
(1) DDR-HSSPI Interface Timing (SDR Mode)
Parameter
HSSPI clock cycle
M_SCLK↑ ->
delayed sample clock↑
M_SDATA -> M_SLCK↑
Input setup time
M_SCLK↑ -> M_SDATA
Input hold time
M_SCLK↑ -> M_SDATA
Output delay time
M_SCLK↑ -> M_SDATA
Output hold time
M_SCLK↑ -> M_SSEL
Output delay time
M_SCLK↑ -> M_SSEL
Output hold time
Notes: This is Target Spec.
−
SS2CD [1:0] should be configured as 01, 10, or 11.
−
For *1, the delay of the delay sample clock can be configured (DLP function).
Document Number: 002-10634 Rev. *J
(T : Recommended operating conditions, Vcc3 = 3.3 V ± 0.3 V, V
A
Symbol Pin Name
t M_SCLK0
cyc
t -
spcnt
M_SDATA0_0-3
t
isdata
M_SDATA1_0-3
M_SDATA0_0-3
t
ihdata
M_SDATA1_0-3
M_SDATA0_0-3
t
oddata
M_SDATA1_0-3
M_SDATA0_0-3
t
ohdata
M_SDATA1_0-3
t M_SSEL0, 1
odsel
t M_SSEL0, 1
ohsel
Conditions
Min
10
20
0
*1
(CL = 20pF,
*1
I = -10mA,
OL
I = 10mA),
OH
-
t /2 - 3
cyc
-
12.00+(SS2
CD+0.5)* t
t - 2
cyc
S6J3350 Series
= DV = AV
SS SS
Value
Unit
Max
-
ns
-
31.5 ns
- ns
- ns
t /2 + 2 ns
cyc
- ns
- ns
cyc
- ns
Page 220 of 307
= 0.0 V)
SS
Remarks
when
Quad Page
Program