Infineon Technologies CYPRESS Traveo Series Manual page 190

Parameter Symbol
Serial clock
t
"H" pulse width
Serial clock
t
"L" pulse width
SCK ↓ -> SOT
t
SLOVE
delay time
Valid SIN -> SCK ↑
t
IVSHE
setup time
SCK ↑ -> Valid SIN
t
SHIXE
hold time
SCK falling time
SCK rising time
*1: n = 0:ch.0 to ch.4, n = 1:ch.8 to ch.12
Notes:
−
This table provides the alternate current standard for CLK synchronous mode.
−
CL is the load capability value connected to the pin at the test time.
−
The maximum baud rate is limited by the internal operating clock used and other parameters.
For details, see the Traveo™ Platform Hardware Manual.
SCK
SOT
SIN
Document Number: 002-10634 Rev. *J
Pin Name
SCK0 to SCK4,
SCK8 to SCK12
SHSL
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12
SLSH
SCK16 to SCK17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SOT0 to SOT4,
SOT8 to SOT12,
SOT16 to SOT17
SCK0 to SCK4,
SCK8 to SCK12,
SCK16 to SCK17
SIN0 to SIN4,
SIN8 to SIN12,
SIN16 to SIN17
SCK0 to SCK4,
t SCK8 to SCK12
F
SCK16 to SCK17
SCK0 to SCK4,
t SCK8 to SCK12
R
SCK16 to SCK17
t
SOVHI
V
OH
V
OL
t
IVSHI
V
IH
V
Conditions
4t
CLK_LCPnA
4t
4t
CLK_LCPnA
4t
Slave
Mode
(CL = 20pF,
I = -5mA,
OL
I = 5mA)
OH
t
SCYC
V
OH
V
OL
t
SHIXI
IL
Master mode
S6J3350 Series
Value
Min Max
*1
-
-
CLK_COMP
*1
-
-
CLK_COMP
- 40
10 -
10 -
- 5
- 5
V
OH
t
SLOVI
V
OH
V
OL
V
IH
V
IL
Unit Remarks
ns
ns
-
ns
ns
ns
ns
ns
ns
ns
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