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Texas Instruments TMS320DM6435Q Manuals
Manuals and User Guides for Texas Instruments TMS320DM6435Q. We have
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Texas Instruments TMS320DM6435Q manual available for free PDF download: Reference Manual
Texas Instruments TMS320DM6435Q Reference Manual (98 pages)
Digital Media Processor DSP Subsystem
Brand:
Texas Instruments
| Category:
Processor
| Size: 0.61 MB
Table of Contents
Table of Contents
3
Preface
9
1 Introduction
11
Introduction
12
Block Diagram
12
Tms320Dm643X DMP Block Diagram
12
DSP Subsystem in Tms320Dm643X DMP
13
Components of the DSP Subsystem
13
2 Tms320C64X+ Megamodule
15
Introduction
16
Tms320C64X+ CPU
16
Tms320C64X+ Megamodule Block Diagram
17
Memory Controllers
18
L1P Controller
18
C64X+ Cache Memory Architecture
19
L1D Controller
20
L2 Controller
20
External Memory Controller (EMC)
21
Internal DMA (IDMA)
21
Internal Peripherals
22
Interrupt Controller (INTC)
22
Power-Down Controller (PDC)
22
Bandwidth Manager
23
3 System Memory
25
Memory Map
26
DSP Internal Memory (L1P, L1D, L2)
26
External Memory
26
Internal Peripherals
26
Device Peripherals
26
Memory Interfaces Overview
27
DDR2 External Memory Interface
27
External Memory Interface
27
4 Device Clocking
29
Overview
30
Clock Domains
30
Core Domains
30
System Clock Modes and Fixed Ratios for Core Clock Domains
30
Overall Clocking Diagram
31
Core Frequency Flexibility
32
Example PLL1 Frequencies and Dividers (27 MHZ Clock Input)
32
DDR2/EMIF Clock
33
Example PLL2 Frequencies (Core Voltage = 1.2V)
33
Example PLL2 Frequencies (Core Voltage = 1.05V)
33
I/O Domains
34
Peripheral I/O Domain Clock
34
Video Processing Back End
35
VPBE/DAC Clocking
35
Possible Clocking Modes
36
5 PLL Controller
37
PLL Module
38
PLL1 Control
38
Device Clock Generation
39
Steps for Changing Pll1/Core Domain Frequency
39
PLL1 Structure in the Tms320Dm643X DMP
39
System PLLC1 Output Clocks
39
PLL2 Control
43
Device Clock Generation
43
PLL2 Structure in the Tms320Dm643X DMP
43
DDR PLLC2 Output Clocks
43
Steps for Changing PLL2 Frequency
44
PLL Controller Registers
48
PLL and Reset Controller List
48
PLL and Reset Controller Registers
48
Peripheral ID Register (PID)
49
Reset Type Status Register (RSTYPE)
49
Peripheral ID Register (PID) Field Descriptions
49
Reset Type Status Register (RSTYPE) Field Descriptions
49
PLL Control Register (PLLCTL)
50
PLL Control Register (PLLCTL) Field Descriptions
50
PLL Multiplier Control Register (PLLM)
51
PLL Controller Divider 1 Register (PLLDIV1)
51
PLL Multiplier Control Register (PLLM) Field Descriptions
51
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
51
PLL Controller Divider 2 Register (PLLDIV2)
52
PLL Controller Divider 3 Register (PLLDIV3)
52
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
52
PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
52
Oscillator Divider 1 Register (OSCDIV1)
53
Oscillator Divider 1 Register (OSCDIV1) Field Descriptions
53
Bypass Divider Register (BPDIV)
54
Bypass Divider Register (BPDIV) Field Descriptions
54
PLL Controller Command Register (PLLCMD)
55
PLL Controller Status Register (PLLSTAT)
55
PLL Controller Command Register (PLLCMD) Field Descriptions
55
PLL Controller Status Register (PLLSTAT) Field Descriptions
55
PLL Controller Clock Align Control Register (ALNCTL)
56
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
56
PLLDIV Ratio Change Status Register (DCHANGE)
57
PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
57
Clock Enable Control Register (CKEN)
58
Clock Enable Control Register (CKEN) Field Descriptions
58
Clock Status Register (CKSTAT)
59
Clock Status Register (CKSTAT) Field Descriptions
59
SYSCLK Status Register (SYSTAT)
60
SYSCLK Status Register (SYSTAT) Field Descriptions
60
6 Power and Sleep Controller
61
Introduction
62
Power and Sleep Controller (PSC) Integration
62
Power Domain and Module Topology
63
Dm643X DMP Default Module Configuration
63
Power Domain and Module States
64
Module States
64
Power Domain States
64
Local Reset
65
Executing State Transitions
65
Module State Transitions
65
Power Domain State Transitions
65
Icepick Emulation Support in the PSC
66
PSC Interrupts
66
Interrupt Events
66
Icepick Emulation Commands
66
PSC Interrupt Events
66
Interrupt Registers
67
Interrupt Handling
68
PSC Registers
68
Power and Sleep Controller (PSC) Registers
68
Peripheral Revision and Class Information Register (PID)
69
Interrupt Evaluation Register (INTEVAL)
69
Peripheral Revision and Class Information Register (PID) Field Descriptions
69
Interrupt Evaluation Register (INTEVAL) Field Descriptions
69
Module Error Pending Register 1 (MERRPR1)
70
Module Error Clear Register 1 (MERRCR1)
70
Module Error Pending Register 1 (MERRPR1) Field Descriptions
70
Module Error Clear Register 1 (MERRCR1) Field Descriptions
70
Power Domain Transition Command Register (PTCMD)
71
Power Domain Transition Status Register (PTSTAT)
71
Power Domain Transition Command Register (PTCMD) Field Descriptions
71
Power Domain Transition Status Register (PTSTAT) Field Descriptions
71
Power Domain Status 0 Register (PDSTAT0)
72
Power Domain Status 0 Register (PDSTAT0) Field Descriptions
72
Power Domain Control 0 Register (PDCTL0)
73
Power Domain Control 0 Register (PDCTL0) Field Descriptions
73
Module Status N Register (Mdstatn)
74
Module Status N Register (Mdstatn) Field Descriptions
74
Module Control N Register (Mdctln)
75
Module Control N Register (Mdctln) Field Descriptions
75
7 Power Management
77
Overview
78
PSC and PLLC Overview
78
Power Management Features
78
Clock Management
79
Module Clock Frequency Scaling
79
Module Clock ON/OFF
79
PLL Bypass and Power down
79
DSP Sleep Mode Management
80
DSP Module Clock ON/OFF
80
DSP Sleep Modes
80
I/O Power down
81
Video DAC Power down
81
8 Interrupt Controller
83
9 System Module
85
Overview
86
Device Identification
86
Device Configuration
86
Pin Multiplexing Control
86
Device Boot Configuration Status
86
I/O Power-Down Control
87
Peripheral Status and Control
87
Timer Control
87
VPSS Clock and DAC Control
87
DDR2 VTP Control
87
HPI Control
87
Bandwidth Management
88
Bus Master DMA Priority Control
88
Tms320Dm643X DMP Master Ids
88
EDMA Transfer Controller Configuration
89
Boot Control
89
Tms320Dm643X DMP Default Master Priorities
89
Reset
91
Overview
92
Reset Pins
92
Device Configurations at Reset
92
10 Reset
92
Reset Types
92
DSP Reset
93
DSP Local Reset
93
DSP Module Reset
93
11 Boot Modes
95
A Revision History
97
Document Revision History
97
Important Notice
98
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