Clock Generation - Xilinx AC701 User Manual

Chapter 1: AC701 Evaluation Board Features
The JTAG connectivity on the AC701 board allows a host computer to download bitstreams to the
FPGA using Xilinx software tools. In addition, the JTAG connector allows debug tools or a software
debugger to access the FPGA. Xilinx software tools can also indirectly program the Quad SPI flash
memory. To accomplish this, Xilinx software configures the FPGA with a temporary design to
access and program the Quad SPI flash memory device. The JTAG circuit is shown in
X-Ref Target - Figure 1-9
VCC3V3
U26
Digilent
USB-JTAG
Module
R95 15Ω
TDI
R96 15Ω
TMS
R94 15Ω
TCK
TDO
VCC3V3
J4
JTAG
Header
JTAG_TDI
TDI
JTAG_TMS
TMS
JTAG_TCK
TCK
JTAG_TDO
TDO

Clock Generation

There are three clock sources available for the FPGA logic on the AC701 board (see
Table 1-8: AC701 Board Clock Sources
FPGA Schematic Net
Pin (U1) Name
R3 SYSCLK_P
P3 SYSCLK_N
24
Send Feedback
U19
SN74LV541A
Buffer
Figure 1-9: JTAG Circuit
Clock
I/O Standard
Reference
LVDS_25
U51
LVDS_25
www.xilinx.com
VCC3V3
FMC1_HPC_PRSNT_M2C_B
U27
Pin Description
4 SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator
(SiTime). See System Clock
5
Figure
J30
FMC1 HPC
Connector
PRSNT_L
FMC_TDI_BUF
TDI
FMC1_TDO_FPGA_TDI
TDO
FMC1_HPC_TMS_BUF
TMS
FMC1_HPC_TCK_BUF
TCK
U1
Artix-7
FPGA
Bank 14
N16
Bank 0
FPGA_TDI_BUF
TDI
FPGA_TCK_BUF
TCK
FPGA_TMS_BUF
TMS
FPGA_TDO
TDO
UG952_c1_09_101512
Table 1-8).
Source.
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
1-9.