Xilinx AC701 User Manual page 55

Table 1-24
Table 1-24: GPIO Connections to FPGA U1
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
lists the GPIO Connections to FPGA U1.
FPGA Pin (U1) Schematic Net Name
M26 GPIO_LED_0
T24 GPIO_LED_1
T25 GPIO_LED_2
R26 GPIO_LED_3
User Directional Pushbutton Switches (Active High)
P6 GPIO_SW_N
U5 GPIO_SW_E
T5 GPIO_SW_S
R5 GPIO_SW_W
U6 GPIO_SW_C
User CPU_RESET Pushbutton Switch (Active High)
U4 CPU_RESET
User 4-Pole DIP Switch (Active High)
R8 GPIO_DIP_SW0
P8 GPIO_DIP_SW1
R7 GPIO_DIP_SW2
R6 GPIO_DIP_SW3
User Rotary Encoder Switch (Active High)
P20 ROTARY_INCB
N21 ROTARY_PUSH
N22 ROTARY_INCA
T8 USER_SMA_GPIO_P
T7 USER_SMA_GPIO_N
User GPIO PMOD Male Pin Header
P26 PMOD_0
T22 PMOD_1
R22 PMOD_2
T23 PMOD_3
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I/O Standard
User LEDs (Active High)
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
SSTL15
LVCMOS33
LVCMOS33
LVCMOS33
User SMA Connectors
SSTL15
SSTL15
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
Feature Descriptions
GPIO Component Pin
DS2.2
DS3.2
DS4.2
DS5.2
SW3.3
SW4.3
SW5.3
SW7.3
SW6.3
SW8.3
SW2.1
SW2.2
SW2.3
SW2.4
SW10.6
SW10.5
SW10.1
J33.1
J34.1
J48.1
J48.2
J48.3
J48.4
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