Xilinx AC701 User Manual page 59

•
•
•
•
Note:
power sequencing logic described in
Table 1-26: HPC Connections, J30 to FPGA U1
J30 FMC1
Schematic Net Name
HPC Pin
A2 FMC1_HPC_DP1_M2C_P
A3 FMC1_HPC_DP1_M2C_N
A6 NC
A7 NC
A10 NC
A11 NC
A14 NC
A15 NC
A18 NC
A19 NC
A22 FMC1_HPC_DP1_C2M_P
A23 FMC1_HPC_DP1_C2M_N
A26 NC
A27 NC
A30 NC
A31 NC
A34 NC
A35 NC
A38 NC
A39 NC
C2 FMC1_HPC_DP0_C2M_P
C3 FMC1_HPC_DP0_C2M_N
C6 FMC1_HPC_DP0_M2C_P
C7 FMC1_HPC_DP0_M2C_N
C10 FMC1_HPC_LA06_P
C11 FMC1_HPC_LA06_N
C14 FMC1_HPC_LA10_P
C15 FMC1_HPC_LA10_N
C18 FMC1_HPC_LA14_P
C19 FMC1_HPC_LA14_N
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
4 GTP transceivers
2 GTP transceiver clocks
2 differential clocks
159 ground and 15 power connections
The AC701 board VADJ voltage for HPC connector J30 is determined by the FMC VADJ
FPGA
I/O Standard
(U1) Pin
(1)
AC14
(1)
AD14
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
(1)
AC8
(1)
AD8
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
(1)
AE9
(1)
AF9
(1)
AE13
(1)
AF13
LVCMOS25 G19
LVCMOS25 F20
LVCMOS25 A17
LVCMOS25 A18
LVCMOS25 C21
LVCMOS25 B21
www.xilinx.com
Power Management.
J30 FMC1
Schematic Net Name
HPC Pin
B1 NC
B4 NC
B5 NC
B8 NC
B9 NC
B12 NC
B13 NC
B16 NC
B17 NC
B20 FMC1_HPC_GBTCLK1_M2C_P
B21 FMC1_HPC_GBTCLK1_M2C_N
B24 NC
B25 NC
B28 NC
B29 NC
B32 NC
B33 NC
B36 NC
B37 NC
B40 NC
D1 CTRL2_PWRGOOD
D4 FMC1_HPC_GBTCLK0_M2C_P
D5 FMC1_HPC_GBTCLK0_M2C_N
D8 FMC1_HPC_LA01_CC_P
D9 FMC1_HPC_LA01_CC_N
D11 FMC1_HPC_LA05_P
D12 FMC1_HPC_LA05_N
D14 FMC1_HPC_LA09_P
D15 FMC1_HPC_LA09_N
D17 FMC1_HPC_LA13_P
Feature Descriptions
FPGA
I/O Standard
(U1) Pin
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA U4.27
NA U4.25
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
NA NA
LVCMOS25 P15
NA U3.27
NA U3.25
LVCMOS25 E17
LVCMOS25 E18
LVCMOS25 G15
LVCMOS25 F15
LVCMOS25 E16
LVCMOS25 D16
LVCMOS25 B20
59
Send Feedback