Artix-7 Fpga - Xilinx AC701 User Manual

Table 1-1: AC701 Board Component Descriptions (Cont'd)
Reference
Callout
Designator
35 U3, U4
Notes:
1. Jumper header locations are identified in

Artix-7 FPGA

[Figure
The AC701 board is populated with the Artix-7 XC7A200T-2FBG676C FPGA.
For further information on Artix-7 FPGAs, see 7 Series FPGAs Overview (DS180)
FPGA Configuration
The AC701 board supports two of the five 7 series FPGA configuration modes:
•
•
Each configuration interface corresponds to one or more configuration modes and bus widths as
listed in
respectively, as shown in
X-Ref Target - Figure 1-3
The default mode setting is M[2:0] = 001, which selects Master SPI flash memory at board
power-on. See
Table 1-2: AC701 Board FPGA Configuration Modes
Master SPI flash memory
JTAG
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Component Description
GTP transceiver clock multiplexers
Default Jumper Settings in Appendix
1-2, callout 1]
Master SPI flash memory using the onboard Quad SPI flash memory
JTAG using a standard-A to micro-B USB cable for connecting the host PC to the AC701
board configuration port or by J4 Platform Cable USB/Parallel Cable IV flat cable connector
Table 1-2. The mode switches M2, M1, and M0 are on SW1 positions 1, 2, and 3
Figure
FPGA_M2
FPGA_M1
FPGA_M0
R339
1.21K 1%
1/10W
Figure 1-3: SW1 Default Settings
Configuration Options
Configuration
Mode
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Notes
Micrel SY89544UMG
A.
1-3.
R338 R337
1.21K 1% 1.21K 1%
1/10W 1/10W
for more information about the mode switch SW1.
SW1 DIP switch
Settings (M[2:0])
001
101
Feature Descriptions
Schematic
0381502
Page Number
30
[Ref 2].
FPGA_3V3
SW1
1 6
NC 2 5
3 4
SDA03H1SBD
UG952_c1_03_011713
Bus CCLK
Width Direction
x1, x2, x4 Output
x1 Not applicable
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