Xilinx AC701 User Manual page 18

Chapter 1: AC701 Evaluation Board Features
Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
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Schematic Net
FPGA Pin (U1)
Name
F7 DDR3_D58
F8 DDR3_D59
G8 DDR3_D60
H8 DDR3_D61
D6 DDR3_D62
E6 DDR3_D63
AC6 DDR3_DM0
AC4 DDR3_DM1
AA3 DDR3_DM2
U7 DDR3_DM3
G1 DDR3_DM4
F3 DDR3_DM5
G5 DDR3_DM6
H9 DDR3_DM7
W8 DDR3_DQS0_N
V8 DDR3_DQS0_P
AE5 DDR3_DQS1_N
AD5 DDR3_DQS1_P
AE1 DDR3_DQS2_N
AD1 DDR3_DQS2_P
V2 DDR3_DQS3_N
V3 DDR3_DQS3_P
B1 DDR3_DQS4_N
C1 DDR3_DQS4_P
A5 DDR3_DQS5_N
B5 DDR3_DQS5_P
H4 DDR3_DQS6_N
J4 DDR3_DQS6_P
G7 DDR3_DQS7_N
H7 DDR3_DQS7_P
R2 DDR3_ODT0
U2 DDR3_ODT1
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J1 DDR3 Memory
I/O Standard
Pin Number
SSTL15 191
SSTL15 193
SSTL15 180
SSTL15 182
SSTL15 192
SSTL15 194
SSTL15 11
SSTL15 28
SSTL15 46
SSTL15 63
SSTL15 136
SSTL15 153
SSTL15 170
SSTL15 187
SSTL15 10
SSTL15 12
SSTL15 27
SSTL15 29
SSTL15 45
SSTL15 47
SSTL15 62
SSTL15 64
SSTL15 135
SSTL15 137
SSTL15 152
SSTL15 154
SSTL15 169
SSTL15 171
SSTL15 186
SSTL15 188
SSTL15 116
SSTL15 120
UG952 (v1.4) August 6, 2019
Pin Name
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0_N
DQS0_P
DQS1_N
DQS1_P
DQS2_N
DQS2_P
DQS3_N
DQS3_P
DQS4_N
DQS4_P
DQS5_N
DQS5_P
DQS6_N
DQS6_P
DQS7_N
DQS7_P
ODT0
ODT1
AC701 Evaluation Board