Xilinx AC701 User Manual page 3

Date Version
04/07/2015 1.3 Replaced the board photo in
clock multiplexers in
banks 32, 33, and 34 with banks 33, 34, and 35 in
Figure
note to
Figure
device types and footnotes in
Changed Texas Instruments parts numbers to LMZ31710 and LMZ31704 in
XADC_GPIO_3, 2, 1, 0 description in
out in
Regulatory and Compliance
08/06/2019 1.4 Updated
Appendix F, Regulatory and Compliance
UG952 (v1.4) August 6, 2019
Figure 1-2
Table 1-1. Replaced
1-10. Major revision of GTP Transceiver Clock Multiplexer
Table 1-13. Replaced Table
1-42. Voltage regulators changed in section
Table 1-27
Table A-3. Updated the Artix-7 FPGA AC701 Declaration of Conformity link in
Information.
DDR3 Memory Module section. Changed
www.xilinx.com
Revision
with the Rev 2.0 board. Added callout row to GTP transceiver
Table 1-4, Table 1-5, Table
DDR3 Memory Module, page
1-16, Table 1-19, Table 1-21,
AC701 Board Power System, page
to reflect device changes. Updated
Table 1-35. Added Figure A-3
Appendix C, Xilinx Design
Information.
1-7, and Table 1-8. Replaced I/O
15. Updated
section, starting on page 28. Added
Table 1-23, and Table 1-26. Updated
67. Updated
Figure 1-44 and Figure
[Ref 22]. Changed
to show board components called
Appendix F,
Constraints. Updated the
AC701 Evaluation Board
1-45.