Xilinx AC701 User Manual page 33

GTP Transceiver Clock Multiplexer Input Clock Sources
This section describes the GTP 213 Multiplexer U3 and U4 input clock circuits as listed in
Table
U3 IN0: 125 MHz Clock Generator
[Figure
Clock Multiplexer U3 IN 0 (pin 4 P, pin 2 N) is driven by U2 ICS84402I Crystal-to-LVDS clock
generator. This device uses 25 MHz crystal X3 as its base input frequency and, using an internal
VCO, multiplies this by five to produce a 0.45 ps (typical) RMS phase jitter, 125 MHz LVDS
output. The circuit for the 125 MHz clock is shown in
X-Ref Target - Figure 1-17
C300
18pF 50V
NPO
X3
R320 2
GND1
1.0M 5%
4
GND2
C301
18pF 50V
NPO
GND_EPHYCLK GND_EPHYCLK
Figure 1-17: AC701 Board 125 MHz U3 MUX IN0 Source Circuit
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
1-11.
1-2, callout 15]
VDDA_EPHYCLK
25.00 MHz
50 ppm
EPHYCLK_XTAL_OUT
X1 1
EPHYCLK_XTAL_IN
3
X2
GND_EPHYCLK
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Figure 1-17.
VDD_EPHYCLK
U2
ICS844021I
1 8
VDDA VDD
EPHYCLK_Q0_C_P
2 7
GND Q0
3 6
XTAL_OUT NQ0
EPHYCLK_Q0_C_N
4 5
XTAL_IN OE
Feature Descriptions
R486
0Ω 5%
EPHYCLK_Q0_P
EPHYCLK_Q0_N
R487
0Ω 5%
UG952_c1_13_101512
33
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