Default Jumper Settings - Xilinx AC701 User Manual

Default Jumper Settings

The AC701 board default jumper configurations are listed in
header locations are shown in
Table A-3: AC701 Default Jumper Settings
Header Ref
Callout
Des
1 J3
2 J5
3 J6
4 J8
5 J9
6 J10
7 J11
8 J52
9 J53
10 J63
11 J35
12 J36
13 J37
14 J38
15 J39
16 J42
17 J43
18 J54
19 J12
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Figure
Jumper
Position
2-pin
None SPI SELECT = onboard SPI flash memory device
1-2 EPHY U12.2 CONFIG2 = LOW
1-2 P3 SFP+ TX enabled
1-2 VCCO_VADJ (FMC) voltage = ON
1-2 U35 REF3012 XADC_AGND L3 bypassed
1-2 U35 REF3012 XADC_AGND = GND
1-2 XADC V
CCINT
None J52.1 INIT_B, J51.2 DONE test header, not a jumper
1-2 XADC_VCC5V0 = 5V
None Voltage regulators enabled
3-pin
1-2 EPHY U12.3 CONFIG3 = HI
None EPHY U12.2 CONFIG2 option header
None EPHY U12.3 CONFIG3 option header
1-2 SFP RX BW = FULL
1-2 SFP TX BW = FULL
1-2 XADC_VREFP = REF3012 XADC_VREF
2-3 XADC_VCC = ADP123 1.85V
2-3 REF3012 V = XADC_VCC
IN
3-4 PCIE lane width = 4
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Table
A-3.
Description
4A range
2x2
Default Jumper Settings
A-3. The AC701 board jumper
Schematic
0381502 Page
4
15
20
45
29
29
34
7
29
38
15
15
15
20
20
29
29
29
28
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