Pci Express Edge Connector - Xilinx AC701 User Manual

Chapter 1: AC701 Evaluation Board Features

PCI Express Edge Connector

[Figure
The 4-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1
application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal datapaths
have a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair.
The 7 series FPGAs GTP transceivers are used for multi-gigabit per second serial interfaces.
The XC7A200T-2FBG676C FPGA (-2 speed grade) included with the AC701 board supports up to
Gen2 x4.
The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through the
MGTREFCLK0 pins of Quad 216. PCIE_CLK_Q0_P is connected to FPGA U1 pin F11, and the
_N net is connected to pin E11. The PCI Express clock circuit is shown in
X-Ref Target - Figure 1-20
PCIe lane width/size is selected using jumper J12
4-lane (J12 pins 3 and 4) jumpered).
X-Ref Target - Figure 1-21
Table 1-12
For more information, see the 7 Series FPGAs Integrated Block for PCI Express v3.0 Product Guide
(PG054)
38
Send Feedback
1-2, callout 12]
P1
PCI Express
Four-Lane
Edge connector
OE
A12
GND
A13
REFCLK+
A14
REFCLK-
A15
GND
Figure 1-20: PCI Express Clock
PCIE_PRSNT_X1
PCIE_PRSNT_X4
Figure 1-21: PCI Express Lane Size Select Jumper J12
lists the PCIe edge connector connections.
[Ref 9].
www.xilinx.com
C188
0.01μF 25V
X7R
PCIE_CLK_Q0_C_P PCIE_CLK_Q0_P
PCIE_CLK_Q0_C_N PCIE_CLK_Q0_N
C189
0.01μF 25V
X7R
GND
UG952_c1_18_100312
(Figure 1-21). The default lane size selection is
J12
PCIE_PRSNT_B
1 2
3 4
UG952_c1_19_100312
Figure 1-20.
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019