Xilinx AC701 User Manual page 25

Table 1-8: AC701 Board Clock Sources (Cont'd)
FPGA Schematic Net
Pin (U1) Name
M21 USER_CLOCK_P
M22 USER_CLOCK_N
P16 FPGA_EMCCLK
The AC701 clocking diagram is shown in
detailed first after
Transceivers
X-Ref Target - Figure 1-10
Rec_Clock_C_P/N Pins D23,D24
SEP_MGT_CLK_SEL[1:0] Pins C24:B26
PCIE_MGT_CLK_SEL[1:0] Pins C26:A24
User SMA
J31(P)/J32(N)
U40
EMCCLK
90 MHz
U34
SI570
Programmable
Oscillator
Default 156.25 MHz
U2
ICS844021
125 Mhz Clock
U24
I2C or SPI
Si5324
J30
Jitter Attenuator
CLK Multiplier
FMC Connector
X6
Crystal
Oscillator
114.285 MHz
GTP SMA
J25(P)/J26(N)
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Clock
I/O Standard
Reference
LVDS_25
U34
LVDS_25
LVCMOS33 U40
Figure 1-10, followed by the GTP clock sources circuitry descriptions in the
section.
U1
USER_CLOCK_N
Pins J23,H23
Bank 16
Bank 15
FPGA_EMCCLK
Bank 14
Pins 3
Bank 13
Bank 12
USER_CLOCK_N/P
Pins M21,M22
I2C
EPHYCLK_Q0_C_P/N Pins 7,6
SI5324_Out0_C_N/P Pins 29,28
Pins D4,D5
(HPC)
Pins B20,B21
SI532_Out1_C_P/N Pins 35,34
SMA_MGT_REFCLK_P Pin 1,1
Figure 1-10: AC701 Board Clocking Diagram
www.xilinx.com
Pin
4 Si570 3.3V LVDS I2C Programmable Oscillator (Silicon
Labs). Default power-on frequency 156.250 MHz. See
5
Programmable User Clock
SiT8103 3.3V Single-Ended LVCMOS 90 MHz Fixed
3
Frequency Oscillator (SiTime). See
Figure 1-10. The FPGA logic clock source circuits are
PCIE_CLK_Q0_P/N
Artix-7 FPGA
XC7A200T-2FBG676C
Bank 36
GTP Quad
216
Bank 35
Bank 34
Bank 33
GTP Quad
213
Bank 32
0
1
U3
2
3
NC
3
NC
2
U4
1
0
Feature Descriptions
Description
Source.
System Clock Source.
P1
PCI Express
Connector
U51
System CLK
SYSCLK_P/N
Pins R3,P3 200 MHz
UG952_c1_110_012015
Send Feedback
GTP
25