Xilinx AC701 User Manual page 42

Chapter 1: AC701 Evaluation Board Features
The Ethernet connections from the XC7A200T at U1 to the 88E1116R PHY device at U12 are listed
in
Table 1-16: Ethernet PHY U12 Connections to FPGA U1
Ethernet PHY Clock Source
A 25.00 MHz, 50 ppm crystal at X1 is the clock source for the 88E1116R PHY at U12.
shows the clock source.
X-Ref Target - Figure 1-23
42
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Table 1-16 Ethernet PHY Connections to FPGA U1.
Schematic Net
FPGA Pin (U1)
Name
T14 PHY_MDIO
W18 PHY_MDC
U22 PHY_TX_CLK
T15 PHY_TX_CTRL
U16 PHY_TXD0
U15 PHY_TXD1
T18 PHY_TXD2
T17 PHY_TXD3
U21 PHY_RX_CLK
U14 PHY_RX_CTRL
U17 PHY_RXD0
V17 PHY_RXD1
V16 PHY_RXD2
V14 PHY_RXD3
V18 PHY_RESET_B
C406
18pF 50V
NPO
R275
1.0M 5%
C405
18pF 50V
NPO
GND
Figure 1-23: Ethernet PHY Clock Source
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I/O Standard
LVCMOS18
LVCMOS18
LVCMOS18
HSTL
HSTL
HSTL
HSTL
HSTL
LVCMOS18
HSTL
HSTL
HSTL
HSTL
HSTL
LVCMOS18
X1
25.00 MHz
50 ppm
4
X1
3
GND1
NC
GND2 X2 1
2
NC
M88E1116R (U12)
Pin Pin Name
45 MDIO
48 MDC
60 TX_CLK
63 TX_CTRL
58 TXD0
59 TXD1
61 TXD2
62 TXD3
53 RX_CLK
49 RX_CTRL
50 RXD0
51 RXD1
54 RXD2
55 RXD3
10 RESET_B
Figure 1-23
PHY_XTAL_OUT
PHY_XTAL_IN
UG952_c1_21_100312
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019