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Revision History
The following table shows the revision history for this document.
Date
Version
10/23/2012
1.0
Initial Xilinx release.
01/30/2013
1.1
Updated photograph in
Revised last paragraph under
Module, page
MHz Clock Generator, page
Clocks, page
under
row in
Display, page
Figure 1-34, page 53
Board Power System, page 67
paragraph under
page
Compliance
08/28/2013
1.2
Added
AC701 Evaluation Board
Figure 1-2, page 11
DDR3 Memory Module, page
23, third paragraph under
33, first, second and third paragraphs under
35, fourth paragraph under
SFP/SFP+ Connector, page
Table 1-14, page
40. Revised second paragraph and added fourth paragraph under
47. Revised first paragraph under
and
Figure 1-35, page
and section
Power Management, page
82. Updated the
Xilinx Design Constraints in Appendix
Information.
Figure
1-10. Revised
Figure
www.xilinx.com
Revision
to revision 1.0 of the AC701 board. Revised
15, fourth paragraph under
GTP Transceivers, page
PCI Express Edge Connector, page
39. Revised third and fourth rows in
I2C Bus Switch, page
54. Revised
Figure 1-41, page
XADC Power System Measurement, page
62. Revised
Figure 1-49, page
C. Added
1-2,
Figure
1-49, and
Figure
Figure
USB JTAG
35, first paragraph under
U3 IN0: 125
U3/U4 IN2: FMC HPC GBT
38, and the first paragraph
Table 1-13, page 40
and the fifth
LCD Character
49. Added
Figure 1-32, page
57. Added section
AC701
72. Added third
78. Revised
Figure A-2,
Appendix F, Regulatory and
1-50.
UG952 (v1.4) August 6, 2019
1-3.
53,
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