Xilinx AC701 User Manual page 27

The user clock circuit is shown in
X-Ref Target - Figure 1-12
The Silicon Labs Si570 data sheet is available from their website
User SMA Clock Input
[Figure
An external high-precision clock signal can be provided to the FPGA bank 15 by connecting
differential clock signals through the onboard 50Ω SMA connectors J31 (P) and J32 (N). The
differential clock signal names are USER_SMA_CLOCK_P and USER_SMA_CLOCK_N, which
are connected to FPGA U1 pins J23 and H23 respectively. The user-provided differential clock
circuit is shown in
Note:
VCCO_VADJ rail is typically 2.5V, but can be reprogrammed to be either 1.8V or 3.3V. The
USER_SMA_CLOCK_P/N signals should not exceed the VCCO_VADJ voltage (1.8V, 2.5V or 3.3V)
in use.
X-Ref Target - Figure 1-13
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
VCC3V3
R15
4.7KΩ 5%
USER CLOCK SDA
To I 2 C
Bus Switch
USER CLOCK SCL
(U49)
GND
Figure 1-12: User Clock Source
1-2, callout 8]
Figure 1-13.
This user clock is input to FPGA bank 15 which is powered by VCCO_VADJ. The
SMA
Connector
SMA
Connector
Figure 1-13: User SMA Clock Source
www.xilinx.com
Figure 1-12.
U34
Si570
Programmable
Oscillator
1 6
NC VDD
2
OE
7
5 USER CLOCK N
SDA
CLK-
8
4 USER CLOCK P
SCL CLK+
3
GND
J31
USER_SMA_CLOCK_P
J32 GND
USER_SMA_CLOCK_N
GND
UG952_c1_12_100212
Feature Descriptions
VCC3V3
C192
0.01 μF 25V
X7R
GND
10 MHz - 810 MHz
UG952_c1_11_101512
[Ref 21].
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