Xilinx AC701 User Manual page 31

Clock Multiplexer U4 SY89544UMG drives Bank 213 MGTREFCLK1 pins AA11 (P) and
AB11(N). See
Table 1-11: Multiplexer U4 SY89544UMG MGT Clock Inputs
Clock Source
Device Ref Pin
SMA J25 1
SMA J26 1
35
SI5324C-GM U24
34
B20
FMC HPC J30
B21
Not connected
Notes:
1. U4 output clock nets SFP_MGT_CLK0_P/N implement a series 0.1 μF capacitor.
2. SEL[1:0] nets PCIE_MGT_CLK_SEL1 FPGA U1 pin C26 and PCIE_MGT_CLK_SEL0 FPGA U1 pin A24
I/O standard = LVCMOS25 (IOSTANDARD assumes default V
The Multiplexer U4 clock input channel select nets are PCIE_MGT_CLK_SEL[1:0].
Net PCIE_MGT_CLK_SEL1 is wired to FPGA U1 pin C26 and net PCIE_MGT_CLK_SEL0 is
wired to FPGA U1 pin A24 on FPGA U1 Bank 16.
The U4 Multiplexer circuit is shown in
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Table 1-11 for clock Multiplexer U4 connections.
SY89544UMG (U4)
Schematic Net Name
Input
SMA_MGT_REFCLK_P
IN0
SMA_MGT_REFCLK_N
SI5324_OUT1_C_N
IN1
SI5324_OUT1_C_P
FMC1_HPC_
GBTCLK1_M2C_P
IN2
FMC1_HPC_
GBTCLK1_M2C_N
IN3
ADJ
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Schematic Net Name
SEL
Pin Output
[1:0]
4
00
2
32
01
30
10(Q) SFP_MGT_CLK1_P
27
11(QB) SFP_MGT_CLK1_N
10
25
23
11
21
of 2.5V)
Figure 1-16.
Feature Descriptions
FPGA U1 Bank 213
(1)
Pin Pin Name
AA11 MGTREFCLK1P
AB11 MGTREFCLK1N
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