Xilinx AC701 User Manual page 69

Figure 1-44
X-Ref Target - Figure 1-44
U8
UCD90120A
Controller
(Controller 1)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Low Pwr Select
GPIO (Out)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Notes:
1. Capacitors labled C f are bulk filter capacitors.
2. Voltage Sense is connected at point of load.
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
shows the power system for UCD90120A U8 controller #1
+12V
(2)
+12V
(2)
+12V
(2)
+12V
(2)
Figure 1-44: U8 Controller #1 UCD90120A Power System
www.xilinx.com
U49 (1.0V Nom)
LMZ31710
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U53 (1.8V Nom)
LMZ31506
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U54 (1.0V Nom)
LMZ31503
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U55 (1.5V Nom)
LMZ31506
Vin Vout
Input
C f
Filter
EN
V
fb
FB
Feature Descriptions
Rs 5mΩ
VCCINT 1.0V
(1)
C f
Rs 5mΩ
VCCAUX 1.8V
C f
Rs 5mΩ
VCCBRAM 1.0V
C f
Rs 5mΩ
FPGA_1V5 1.5V
C f
UG952_c1_41_030915
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