Xilinx AC701 User Manual page 19

Table 1-4: DDR3 Memory Connections to the FPGA (Cont'd)
The AC701 board DDR3 memory interface adheres to the constraints guidelines documented in the
DDR3 Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide
(UG586)
Other memory interface details are available in the 7 Series FPGAs Memory Interface Solutions
User Guide (UG586) and the 7 Series FPGAs Memory Resources User Guide (UG473)
more DDR3 SODIMM details, see the Micron MT8JTF12864HZ-1G6G1 data sheet
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Schematic Net
FPGA Pin (U1)
Name
N8 DDR3_RESET_B
T3 DDR3_S0_B
T2 DDR3_S1_B
DDR3_TEMP_
U1
EVENT
R1 DDR3_WE_B
T4 DDR3_CAS_B
P1 DDR3_RAS_B
P4 DDR3_CKE0
N4 DDR3_CKE1
L2 DDR3_CLK0_N
M2 DDR3_CLK0_P
N2 DDR3_CLK1_N
N3 DDR3_CLK1_P
4]. The AC701 board DDR3 memory interface is a 40 Ω impedance implementation.
[Ref
www.xilinx.com
J1 DDR3 Memory
I/O Standard
Pin Number
LVCMOS15 30
SSTL15 114
SSTL15 121
LVCMOS15 198
SSTL15 113
SSTL15 115
SSTL15 110
SSTL15 73
SSTL15 74
DIFF_SSTL15 103
DIFF_SSTL15 101
DIFF_SSTL15 104
DIFF_SSTL15 102
Feature Descriptions
Pin Name
RESET_B
S0_B
S1_B
EVENT_B
WE_B
CAS_B
RAS_B
CKE0
CKE1
CK0_N
CK0_P
CK1_N
CK1_P
[Ref 5]. For
[Ref 15].
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