Spi Flash Memory External Programming Header - Xilinx AC701 User Manual

SPI Flash Memory External Programming Header

In addition to the Quad SPI device FPGA U1 connections shown in
flash memory interface is connected to an external programming header J7.
Table 1-6
Table 1-6: SPI Flash Memory J7 Connections to the FPGA
Figure 1-6
X-Ref Target - Figure 1-6
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
shows the SPI flash memory J7 connections to FPGA U1.
U1 FPGA Pin Schematic Net Name
AE16 FPGA_PROG_B
N14 FLASH_D3
P14 FLASH_D2
J3.2 QSPI_CS_B
R14 FLASH_D0
R15 FLASH_D1
H13 FPGA_CCLK
NA
NA VCC3V3
shows the J7 SPI flash memory external programming connector.
J7
1
2
3
4
5
6
7
8
9
HDR
1X9
Figure 1-6: SPI Flash Memory J7 External Programming Connector
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J7 Pin
1
2
3
4
5
6
7
GND 8
9
FPGA_PROG_B
FLASH_D3
FLASH_D2
QSPI_CS_B
FLASH_D0
FLASH_D1
VCC3V3
FPGA_CCLK
GND
UG952_c1_06_092812
Feature Descriptions
Table 1-5, the FPGA U1 SPI
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