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Clock Multiplexer U3 SY89544UMG drives Bank 213 MGTREFCLK0 pins AA13 (P) and AB13
(N).
See
Table 1-10: Multiplexer U3 SY89544UMG MGT Clock Inputs
Clock Source
Schematic Net Name
Device
Ref
Pin
7
ICS84402I
U2
6
29
SI5324C-GM
U24
28
D4
FMC HPC
J30
D5
Not connected
Notes:
1. U3 output clock nets SFP_MGT_CLK0_P/N implement a series 0.1μF capacitor
2. SEL[1:0] nets SFP_MGT_CLK_SEL1 FPGA U1 pin C24 and SFP_MGT_CLK_SEL0 FPGA U1 pin B26.
The I/O standard is LVCMOS25 (IOSTANDARD assumes a default V
The multiplexer U3 clock input channel select nets are SFP_MGT_CLK_SEL[1:0].
Net SFP_MGT_CLK_SEL1 is wired to FPGA U1 pin C24 and net SFP_MGT_CLK_SEL0 is wired
to FPGA U1 pin B26 on FPGA U1 Bank 16.
The U3 multiplexer circuit is shown in
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
Table 1-10
for clock MUX U3 connections.
SY89544UMG U3
SEL
Input
[1:0](2)
EPHYCLK_Q0_P
IN0
EPHYCLK_Q0_N
SI5324_OUT0_C_N
IN1
SI5324_OUT0_C_P
FMC1_HPC_
GBTCLK0_M2C_P
IN2
FMC1_HPC_
GBTCLK0_M2C_N
IN3
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Schematic Net Name
Pin
Output
4
00
2
32
01
30
10(Q)
SFP_MGT_CLK0_P
27
11(QB)
SFP_MGT_CLK0_N
10
25
23
11
21
of 2.5V)
ADJ
Figure
1-15.
Feature Descriptions
FPGA U1 Bank 213
(1)
Pin
Pin Name
AA13
MGTREFCLK0P
AB13
MGTREFCLK0N
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29
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