Xilinx AC701 User Manual page 71

Figure 1-45
X-Ref Target - Figure 1-45
Notes:
U9
1. Capacitors labled C f are bulk filter capacitors.
UCD90120A
2. Voltage Sense is connected
at point of load.
Controller
(Controller 2)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
FMC_ADJ_SEL[1:0]
GPIO (Out)
FMC_ADJ_SEL[1:0]
Value
0 0
0 1
1 0
1 1
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
Rail Enable
GPIO (Out)
PWM Margin
FPWM (Out)
Current Sense
ADC (In)
Voltage Sense
ADC (In)
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
shows the power system for UCD90120A U9 controller #2 rails 1 through 5.
+12V
(2)
VCCO_ADJ
Output
2.5V
1.8V
3.3V
+12V
3.3V
(2)
+12V
(2)
+12V
(2)
+12V
(2)
Figure 1-45: U9 Controller #2 UCD90120A Power System
www.xilinx.com
U56 (2.5V Nom)
LMZ31506
Vin Vout
Input
C f
Filter
EN
V
fb
FB
I0B
U64
YB
I1B
S[1:0]
I2B
I3B
U57 (1.8V Nom)
LMZ31503
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U58 (3.3V Nom)
LMZ31506
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U59 (1.0V Nom)
LMZ31503
Vin Vout
Input
C f
Filter
EN
V
fb
FB
U60 (1.2V Nom)
LMZ31503
Vin Vout
Input
C f
Filter
EN
V
fb
FB
Feature Descriptions
Rs 5mΩ
VCCO_ADJ 2.5V
(1)
C f
VCC1V8 1.8V
(Not measued separately)
Rs 5mΩ
FPGA_1V8 1.8V
C f
VCC3V3 3.3V
(Not measued separately)
Rs 5mΩ
FPGA_3V3 3.3V
C f
Rs 5mΩ
MGTAVCC 1.0V
C f
Rs 5mΩ
MGTAVTT 1.2V
C f
UG952_c1_138_030615
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