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Chapter 1:
AC701 Evaluation Board Features
Configuration Options
The FPGA on the AC701 board can be configured using these methods:
•
•
See
See 7 Series FPGAs XADC Dual 12-Bit 1MSPS Analog-to-Digital Converter User Guide (UG480)
[Ref 10]
The method used to configure the FPGA is controlled by the mode pins (M2, M1, M0) setting
selected through DIP switch SW1.
Table 1-36: Mode Switch SW1 Settings
Master SPI flash memory
JTAG
Figure 1-49
X-Ref Target - Figure 1-49
78
Send Feedback
Master SPI flash memory (uses the Quad SPI flash memory U7).
JTAG (uses the U26 Digilent USB-to-JTAG bridge or J4 download cable connector).
USB JTAG Module
for more information.
for further details on configuration modes.
Configuration
Mode Pins (M[2:0])
Mode
shows mode switch SW1.
FPGA_M2
FPGA_M1
FPGA_M0
www.xilinx.com
Table 1-36
lists the supported mode switch settings.
001
101
SW1
ON
1
NC
2
3
SDA03H1SBD
R339
R337
1.21K
1.21K
0.1W
0.1W
1%
1%
R338
1.21K
0.1 W
1%
GND
Figure 1-49: Mode Switch
Bus
CCLK
Width
Direction
x1, x2, x4
Output
x1
Not applicable
FPGA_3V3
6
5
4
UG952_c1_49_030615
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019
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