Fig. 2.17 Ports 40 To 47, 50 To 57 And 60 To 67; Fig. 2.18 Bz - Fujitsu MB89140 Series Hardware Manual

I/O PORTS
Internal data bus
PDR
PDR read
PDR write
Stop mode (SPL = 1)
Buzzer circuit
Stop mode (SPL = 1)
HARDWARE CONFIGURATION
State in watch mode
When the SPL bit of the standby-control register is set to 1, in the stop
mode, the output impedance goes High irrespective of the value of the
PDR.
Output latch

Fig. 2.17 Ports 40 to 47, 50 to 57 and 60 to 67

(9) BZ: P-ch open-drain high-withstand-voltage output
Buzzer output
A waveform at the frequency set by the buzzer register (BUZR) is output
to the pin.
State when reset
When reset, the buzzer register (BUZR) is initialized to 0 and the output
impedance goes High.
State in Stop mode
With the SPL bit of the standby control register is set to 1, the output im-
pedance goes High irrespective of the BUZR value.

Fig. 2.18 BZ

2-33
Pch
Pin
Pull-down resistor
(Option)
VFDP
Pch
Pin