Fujitsu MB89140 Series Hardware Manual page 71

8/16-BIT TIMER
(TIMER 2 AND TIMER 3)
Address: 0018 T3CR
H
Address: 0019 T2CR
H
Address: 001A T3DR
H
Address: 001B T2DR
H
HARDWARE CONFIGURATION
[bit 1] T3STP: Timer stop bit
Operation continued without clearing counter
0
Count operation suspended
1
[Bit 0] T3STR: Timer start bit
Operation stopped
0
Operation started after clearing counter
1
(3) Timer 1 and 2 data registers (T2DR and T2DR)
Bit 7 Bit 6
Address:
001B
H
Address: (R/W) (R/W)
001A
H
Write data is the set interval times and read data is the counted value.
2-51
Bit 5 Bit 4 Bit 3 Bit 2
(R/W) (R/W) (R/W) (R/W)
Bit 1 Bit 0
(R/W) (R/W)
Initial value
XXXXXXXX
B