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APPENDIX C LIST OF SYSTEM CLOCK CYCLE TIMES WHEN GEAR CHANGED
(Source clock: 8 MHz, 4 MHz)
Setting of CS1 and CSO bits (system clock select bit) of SYCC register
Number of
CS1 = 1, CSO = 1
system
clocks
8 MHz
(µs)
1
0.5
2
1.0
4
2.0
8
4.0
16
8.0
32
16.0
64
32.0
APPENDIX
CS1 = 1, CSO = 0
4 MHz
8 MHz
4 MHz
(µs)
(µs)
(µs)
1.0
1.0
2.0
2.0
4.0
4.0
8.0
8.0
16.0
16.0
32.0
32.0
64.0
64.0
128.0
App.- 7
CS1 = 0, CSO = 1
8 MHz
4 MHz
(µs)
(µs)
2.0
2.0
4.0
4.0
4.0
8.0
8.0
8.0
16.0
16.0
16.0
32.0
32.0
32.0
64.0
64.0
64.0
128.0
128.0
256.0
CS1 = 0, CSO = 0
8 MHz
4 MHz
(µs)
(µs)
8.0
16.0
16.0
32.0
32.0
64.0
64.0
128.0
128.0
256.0
256.0
512.0
512.0
1024.0
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