Fujitsu MB89140 Series Hardware Manual page 36

MAIN/SUBCLOCK
CONTROL BLOCK
HARDWARE CONFIGURATION
(a) WATCH mode
Switching to WATCH mode
– Writing 1 at the TMD bit of the STBC register switches the mode to
WATCH mode. Writing is invalid if 1 is set at the SCS bit (bit 2) of the
SYCC register.
– The WATCH mode stops all chip functions except the watch prescaler,
external interrupt, and wake-up functions. Therefore, data can be held
with the lowest power consumption.
– The input/output pins and output pins during the WATCH mode can be
controlled by the SPL bit of the STBC register so that they are held in
the state immediately before entering the WATCH mode or so that they
enter the high-impedance state.
– If an interrupt is requested when 1 is written at the TMD bit , instruction
execution continues without switching to the WATCH mode.
– In the WATCH mode, the values of registers and RAM immediately be-
fore entering the WATCH mode are held.
Canceling WATCH mode
– The WATCH mode is canceled by inputting the reset signal and re-
questing an interrupt.
– When the reset signal is input during the WATCH mode, the CPU is
switched to the reset state and the WATCH mode is canceled.
– When an interrupt higher than level 11 is requested from a resource
during the WATCH mode, the WATCH mode is canceled.
– When the I flag and IL bit are enabled like an ordinary interrupt after
canceling, the CPU executes the interrupt processing. When they are
disabled, the CPU executes the interrupt processing from the instruc-
tion next to the one before entering the WATCH mode.
– If the WATCH mode is canceled by inputting the reset signal, the CPU
is switched to the oscillation stabilization wait state. Therefore, the re-
set sequence is not executed unless the oscillation stabilization time is
elapsed. The oscillation stabilization time will be that of the main clock
selected by the WT1 and WT0 bits. However, when Power-on Reset is
not specified by the mask option, the CPU is not switched to the oscilla-
tion stabilization wait state, even if the WATCH mode is canceled by
inputting the reset signal.
(b) SLEEP mode
Switching to Sleep mode
– Writing 1 at the SLP bit (bit 6) of the STBC register switches the mode to
SLEEP mode.
– The SLEEP mode is the mode to stop clock pulse operating the CPU;
only the CPU stops and the resources continue to operate.
– If an interrupt is requested when 1 is written at the SLP bit (bit 6),
instruction execution continues without switching to the SLEEP mode.
– In the SLEEP mode, the values of registers and RAM immediately be-
fore entering the SLEEP mode are held.
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