Fujitsu MB89140 Series Hardware Manual page 70

8/16-BIT TIMER
(TIMER 2 AND TIMER 3)
Address: 0018 T3CR
H
Address: 0019 T2CR
H
Address: 001A T3DR
H
Address: 001B T2DR
H
T2CS1 T2CS0
0
0
1
1
Note: When bit 2 and 3 use only timer 2, set this bit to except 11.
HARDWARE CONFIGURATION
[Bit 1] T2STP: Timer-stop bit
0 Counting continued without clearing counter
1 Counting suspended
[Bit 0] T2STR: Timer-start bit
0 Terminates operation
1 Clears counter and starts operation
(2) Timer 3 control register (T3CR)
Bit 7
T3IF
Address: 0018
H
(R/W)
[Bit 7] T3IF: Interrupt request flag bit
(When write)
Interrupt request flag clearing
0
No operation
1
(When read)
No interrupt request
0
Interval interrupt request
1
[Bit 6] T31E: Interrupt-enable bit
Interrupt disabled
0
Interrupt enabled
1
[Bit 5]: Reserved; write 0 when writing.
[Bit 4]: Reserved; write 0 when writing.
[Bit 3 and 2]: T3CS1, T3CS0: Clock source select bit
Time cycle at 8 MHz and
Maximum gear speed
1.0 µs
0
2.0 µs
1
4.0 µs
0
1 16-bit mode
2-50
Bit 6 Bit 5 Bit 4 Bit 3
T3IE — — T3CS1 T3CS0 T3STP T3STR
(R/W) (R/W) (R/W) (R/W)
System clock cycle
2 system clock cycle
4 system clock cycle
8 system clock cycle
Bit 2 Bit 1 Bit 0
(R/W) (R/W) (R/W)
Initial value
X000XXX0
B
—